M2N1G64TUH8D4F / M2N2G64TU8HD4B / M2N1G64TUH8D5F / M2N2G64TU8HD5B
M2N1G64TUH8D6F / M2N2G64TU8HD6B
1GB: 128M x 64 / 2GB: 256M x 64
Unbuffered DDR2 SO-DIMM
REV 1.1 9
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Serial Presence Detect (2GB – 2 Ranks, 128Mx8 DDR2 SDRAMs) (Part 1 of 2)
Serial PD Data Entry (Hex.)
Number of Serial PD Bytes Written during Production
Total Number of Bytes in Serial PD device
Number of Row Addresses on Assembly
Number of Column Addresses on Assembly
Number of DIMM Ranks, Package, and Height
Module Height = 30.0mm, 2 ranks
Voltage Interface Level of this Assembly
DDR2 SDRAM Device Cycle Time at CL=5
DDR2 SDRAM Device Access Time (t
ac
) from Clock
at CL=5
Non Address/Command Parity,
Non Data ECC,
Non Data Parity,
Error Checking DDR2 SDRAM Device Width
DDR2 SDRAM Device Attributes: Burst Length
Supported
DDR2 SDRAM Device Attributes: Number of Device
Banks
DDR2 SDRAM Device Attributes: Latencies
Supported
DIMM Mechanical Characteristics
DDR2 SDRAM DIMM Type Information
DDR2 SDRAM Module Attributes
Analysis probe installed : No,
FET Switch External Enable : No,
Number of PLLs : 0,
Number of Active Registers : 1,
DDR2 SDRAM Device Attributes: General
Supports Weak Driver,
Supports 50 ohm ODT,
Supports PASR,
Minimum Clock Cycle at CL=4
Maximum Data Access Time from Clock at CL=4
Minimum Clock Cycle Time at CL=3
Maximum Data Access Time from Clock at CL=3
Minimum Row Precharge Time (t
RP
)
Minimum Row Active to Row Active delay (t
RRD
)
Minimum to delay (t
RCD
)
Minimum Active to Precharge Time (t
RAS
)
Address and Command Setup Time Before Clock
(t
IS
)
Address and Command Hold Time After Clock (t
IH
)
Data Input Setup Time Before Clock (t
DS
)
Data Input Hold Time After Clock (tDH)
Write Recovery Time (t
WR
)
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