CnMemory M2N2G64TU8HD5B-AC Datasheet download pdf (Page 9)

M2N1G64TUH8D4F / M2N2G64TU8HD4B / M2N1G64TUH8D5F / M2N2G64TU8HD5B

M2N1G64TUH8D6F / M2N2G64TU8HD6B

1GB: 128M x 64 / 2GB: 256M x 64

Unbuffered DDR2 SO-DIMM

REV 1.1 9

07/2008

NANYA reserves the right to change products and specifications without notice.

Serial Presence Detect (2GB – 2 Ranks, 128Mx8 DDR2 SDRAMs) (Part 1 of 2)

Byte

Description

SPD Entry Value

Serial PD Data Entry (Hex.)

Note

-3C

-AC

-3C

-AC

Number of Serial PD Bytes Written during Production

128

Total Number of Bytes in Serial PD device

256

Fundamental Memory Type

DDR2 SDRAM

Number of Row Addresses on Assembly

Number of Column Addresses on Assembly

Number of DIMM Ranks, Package, and Height

Module Height = 30.0mm, 2 ranks

Data Width of Assembly

X64

Reserved

Undefined

Voltage Interface Level of this Assembly

SSTL 1.8V

DDR2 SDRAM Device Cycle Time at CL=5

3ns

2.5ns

DDR2 SDRAM Device Access Time (t

) from Clock

at CL=5

0.45ns

0.4ns

DIMM Configuration Type

Non Address/Command Parity,

Non Data ECC,

Non Data Parity,

Refresh Rate/Type

7.8 μs

Primary DDR2 SDRAM Width

Error Checking DDR2 SDRAM Device Width

Undefined

Reserved

Undefined

DDR2 SDRAM Device Attributes: Burst Length

Supported

4,8

DDR2 SDRAM Device Attributes: Number of Device

Banks

DDR2 SDRAM Device Attributes:  Latencies

Supported

3,4,5

DIMM Mechanical Characteristics

x ≤ 3.80 (mm)

DDR2 SDRAM DIMM Type Information

SO-DIMM (67.6mm)

DDR2 SDRAM Module Attributes

Analysis probe installed : No,

FET Switch External Enable : No,

Number of PLLs : 0,

Number of Active Registers : 1,

DDR2 SDRAM Device Attributes: General

Supports Weak Driver,

Supports 50 ohm ODT,

Supports PASR,

Minimum Clock Cycle at CL=4

3.75ns

Maximum Data Access Time from Clock at CL=4

0.5ns

Minimum Clock Cycle Time at CL=3

5ns

Maximum Data Access Time from Clock at CL=3

0.6ns

Minimum Row Precharge Time (t

)

15ns

12.5ns

Minimum Row Active to Row Active delay (t

RRD

)

7.5ns

Minimum  to  delay (t

RCD

)

15ns

12.5ns

Minimum Active to Precharge Time (t

RAS

)

45ns

Module Rank Density

1GB

Address and Command Setup Time Before Clock

)

0.2ns

0.17ns

Address and Command Hold Time After Clock (t

)

0.27ns

0.25ns

Data Input Setup Time Before Clock (t

)

0.1ns

0.05ns

Data Input Hold Time After Clock (tDH)

0.17ns

0.12ns

Write Recovery Time (t

)

15ns

1 2 3 4 5 6 7 8 9 10 11 12 13 14 ... 18 19

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CnMemory M2N2G64TU8HD5B-AC Datasheet Page 9

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